VP primer


This 1-day training introduces the student to the foundations of Virtual Platform (VP) modeling and deployment. It is intended for engineers who are new to or interested in learning about VP modeling. The student will learn how to write and debug VPs, as well as which features are typically need for a successful VP deployment. The focus is on providing an overview over different components, tools and techniques. The training is agnostic with regards to tool or IP vendors. This course is a mix of lecture and exercises. The exercises will be shown as demos, but the student will have access to all material in order to follow along or repeat exercises later.



o Overview

o What is a VP? Virtual prototype versus Virtual platform

o How do VPs fit into the SoC development cycle?

Modeling techniques

o Behavioral/untimed

o Functional/loosely timed

o Cycle-accurate/approximately timed

o Register-transfer-level


o C++/SystemC,/TLM2

o Register modeling e.g. IP-XACT, RDL

o Productivity libraries, e.g. SCML

o Commonly used open source libraries

IP for VP development

o Typical building blocks of a VP


? Peripherals

? Interconnects

o Commercial 3rd party IPs e.g. ARM, Synopsys, Cadence

o Make versus open source versus buy

Tools for VP development

o Commercial tools, e.g. Virtualizer, SoC Designer, VLAB Works

o Open source tools

o Connections to other environments

o Pitfalls

Putting it all together

o Setting up an example VP

o Debug & analysis

o Debugging the VP itself

o Debugging SW/FW components running on a VP

o Infrastructure, e.g. test-driven development (TDD), continuous integration (CI)

o Configuration

Addressing typical requirements for VP deployment

o Simulation speed

o Scalability, e.g. extensibility, documentation, usage model, packaging

o Observability. E.g. TLM recording, logging, data visualization

o Accuracy


Basic knowledge of C/C++, SystemC and TLM2


Engineers who are new to or interested in learning about VP modeling

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