The MPC5777M Power Architecture® MCU targets high-end industrial and powertrain applications that meet next-generation advanced engine control, functional safety, and security requirements. It provides task flexibility and parallel processing by leveraging the I/O processor to offload computational cores. Also deters software hacking and aftermarket tuning (which affects unauthorized warranty returns) with next-generation security protection.

Course Agenda :

• Overview of the MPC5777C silicon systems and MPC57xx Roadmap.

• Understand the e200z7 programming models, register types, and usages.

• Learn the e200z7 instruction sets, branches, subroutine calls simplified mnemonics, accessing operands in memory, and lock-step core options.

• Configure and optimize the core I-cache and D-cache to improve system performance.

• Configure the e200z7 Memory Management Unit (MMU) for address translation, access control, and memory protections.

• Write efficient exception service routines and configure the Programmable Interrupt Controller (PIC) by understanding the innovative exception processing function with built-in interrupt priorities, separate critical, non-critical, and machine check interrupts.

• Understand Boot-Assist Module (BAM) and different ways of handling sources of system reset.

• Configure and initialize the External Bus Interface (EBI), including memory controller.

• Configure and initialize the enhanced DMA (eDMA) to transfer data between I/O peripherals and memory via the crossbar switch (XBAR).

• Learn how to initialize the enhanced MIOS (eMIOS) for various timer modes to drive actuators, motors, and monitor input signals.

• Configure and initialized the enhanced QADC (eQADC) to measure analog signals using various scan modes, various trigger mechanisms, various interrupt schemes, and various digital data formats.

• Configure and initialize the popular communication modules such as Fast Ethernet Controller (FEC), FlexCAN, eSCI, and LIN interface.

• Learn how to initialize the enhanced MIOS (eMIOS) for various timer modes to drive actuators, motors, and monitor input signals.

• Understand and configure the enhanced TPU (eTPU) timing functions enables more sophisticated timing functions and simplify angle domain scheduling using its powerful angle clock hardware.

• In-depth understanding of Functional Safety which includes two cores running in lock-step for safety integrity, Fault Control and Collection Unit (FCCU), Self-Test Control Unit (STCU2) and meeting the ASIL 26262 Standards.

• And much more...


Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.


The MPC5777C architectural training course is designed for software, hardware, firmware, test engineers, and developers who want to build engine controller and industrial control system applications. System architects, project leaders, and BSP designers, device driver designers, test engineers who want to understand device architecture and requirements are also encourage to attend the this class for an in-depth understanding of the silicon system.

Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device.

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