MPC5746M (McKinley) PowerPC Multi-Core Architecture


Course Title: MPC5746M (McKinley) PowerPC Multi-Core Architecture

Target Applications: Automotive, aerospace, industrial, and commercial.

Course Description:

This 4 day course offers in-depth overview of the Multi-Core MPC5746M device. Full coverage of the on-chip PowerPC cores is provided including Power Architecture main features, operation and Programming. It covers the on-chip tightly-coupled memories including instruction and data caches, core memory management unit (CMPU), system memory protection Unit (SPMU), Low power management, system Integration and chip pad configuration, system exception, Interrupt controller and external interrupts, boot assist Flash (BAF) and startup sequence for all on-chip processor cores, semaphore unit (SEM4) which allows sharing of system resources to ensure data integrity and coherency, cross-bar switches to support simultaneous multi-master to multi-slave accesses. Details of most of on-chip peripherals, such Deserial Serial Peripheral Interface (DSPI), micro-second channel (TSB), eDMA multiplexers and eDMA engine, serial interfaces, periodic interrupt timers (PITs), system timers (STMs), watchdog timers (WDGs). It also covers the multiple on-chip SAR_ADCs and SD_ADCs including trigger signals from GTM and other external signals. Full details of the Generic Timer Module (GTM) will be covered with hands-on Labs.

Those who interested in meeting the Automotive Integrity Level (ASIL 26262) safety standards will benefit from attending this training.

Participants will be provided: A hard copy of the workshop course notes, lab book and textbook. A CDROM of all the example software projects and demo version of the development tools is also provided.

After completing the workshop, the participant will understand the basic concepts of this quad core device and all major functional blocks.


Day 1

MPC5746M Overview

• Main Features and System Architecture

• On-chip tightly-coupled memories including instruction and data caches

• Level 2 memory organization and operation

• Power architecture coresprogramming Model that covers (e200z419/z420 and z425 cores including variable-length encoding (VLE) and light signal processing unit (LSP)

• Core memory protection unit (CMPU)

• Crossbar switches and bus master arbitration sequence

• System memory protection unit (SMPU)

• Power Architecture Exceptions and Interrupts

Day 2

• Interrupt controller, architectural features and startup sequence

• Interrupt Controller and Context Switching (New Instructions)

• Semaphore Block

• System Clock Generation and PLL operation

• Pad (Pin) assignment and configuration

• Boot-assist Flash (BAF boot sequence)

• System Reset Sources and Reset Handling

• Device configuration and system initialization at startup

• Power Modes

• DMA_Multiplexers

• eDMA functional description and programming

Day 3

Serial Interfaces


• Microsecond channel (TSB)

• CRC genertaor

• Introduction to FlexRay



Functional Safety

• Introduction to Functional Safety

• Fault Control and Collection Unit (FCCU)

• Self Test Control Unit (STCU2)

• Meeting ASIL 26262 Standards

Day 4

Memories, Analog and system timers

• Flash and SRAM

• Error Correction Code

• Software Watchdog Timers (SWT)

• System Timers (STM)

• SAR_ADCs and SD_ADC architecture and operation

• System timers (STMs), periodic interrupt timers (PITs) and watchdog

• Generic Timer Module (GTM)


• Nexus Summary


Knowledge/experience of some microprocessor/microcontroller is necessary


Software and system engineers who need to come up to speed quickly on how to program and design with the MPC5746M Device.

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