MPC5700 Family (English)


System designer (especially power train), System programmer, Application programmer, Embedded programmer and System tester.


  • Part 1 - MPC5777 Overview
    • MPC5700 Family Roadmap
    • Main Features and System Architecture
    • On-chip tightly-coupled memories including instruction and data caches
    • Level 1 and level 2 memory organization and operation
    • Power architecture cores programming Model that covers (e200z7 and z425) cores including variable-length encoding (VLE) and light signal processing unit (LSP)
    • Core memory protection unit (CMPU)
    • Crossbar switches and bus master arbitration sequence
    • System memory protection unit (SMPU)
    • Power Architecture Exceptions and Interrupts
  • Part 2 - Interrupt controller, architectural features and startup sequence
    • Interrupt Controller and Context Switching (New Instructions)
    • Semaphore Block
    • System Clock Generation and PLL operation
    • Pad (Pin) assignment and configuration
    • Boot-assist Flash (BAF boot sequence); SW init check list
    • System Reset Sources and Reset Handling
    • Device configuration and system initialization at startup
    • Mode Entry Module (Low power and run modes)
    • DMA_Multiplexers
    • eDMA functional description and programming
  • Part 3 - Serial Interfaces
    • DSPI, Microsecond channel (TSB)
    • CRC generator
    • Introduction to FlexRay
  • Part 3 - Memories, Analog and system timers
    • Flash and SRAM
    • Flash organization and programming
    • Error Correction Code
    • Software Watchdog Timers (SWT)
    • System Timers (STM)
    • SAR_ADCs and SD_ADC architecture and operation
    • System timers (STMs), periodic interrupt timers (PITs) and watchdog
  • Part 3 - Generic Timer Module (GTM)
    • Timer overview
    • Timer Input Module (TIM)
    • Timer Output Module (TOM)
    • ARU connected Timer Out Module (ATOM)
    • Basic Operation and Programming
    • Angle Clock Generation and Operation
    • Examples
  • Part 3 - Functional Safety
    • Introduction to Functional Safety
    • 2 cores running in Lock-step for safety Integrity
    • Fault Control and Collection Unit (FCCU)
    • Self Test Control Unit (STCU2)
    • Meeting ASIL 26262 Standards
  • Part 3 - Tools
    • Nexus / Aurora Differences / Summary


Knowledge in C programming.


System designer (especially power train), System programmer, Application programmer, Embedded programmer and System tester.

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