MPC564xA(Andorra)

Kursbeschreibung

Course Title:MPC564xA(Andorra)

Course Agenda:

The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

Overview of the MPC5644A and MPC5642A silicon systems and Roadmap.

Learn the latest e200z4 Power Architecture programming model, register types, Single Instruction Multiple Data (SIMD), and Variable Length Encoding (VLE)

Review e200z4 core instruction set, branches, subroutine calls, simplified mnemonics, including the new SPE instruction features.

Write efficient exception service routines for the e200z7 core and Interrupt Controller (INTC) by understanding the innovative exception processing function with built-in interrupt priorities, separate critical, non-critical resources using HW or SW vector mode.

Configure and optimize the e200z4 L1 cache with new APU cache locking instructions.

Initialize the improved and simplified Memory Management Unit (MMU) to perform address translation, access control, and protection.

Configure and initialize the External Bus Interface (EBI), including memory controller, bus monitor, arbiter and various external pins needed to communicate to external peripherals.

Understand and configure some of the enhanced TPU (eTPU) timing functions with new and easy C-like instructions. The eTPU enables more sophisticated timing functions and simplify angle domain scheduling using its powerful angle clock hardware.

Learn how to initialize the enhanced MIOS (eMIOS) for various timer modes to drive actuators, motors, and monitor input signals.

Configure and initialize the enhanced DMA (eDMA) to transfer data between on-chip I/O peripherals and on-chip memory via the crossbar switch (XBAR). eDMA module does not have external pins.

Configure and initialized the enhanced QADC (eQADC) to measure analog signals using various scan modes, various trigger mechanisms, various interrupt schemes, and various digital data formats. Independent eADCs with up to 12-bit A/D resolution.

Configure and initialize some of the serial channel communication such as enhanced SCI (eSCI) and the DSPI.

Configure and initialize the popular FlexCAN a serial communication protocols used for automotive and industrial control applications.

Learn how to initialize from power-on reset. Understand and use the Boot Assist Module (BAM) for device operation after reset, but before user application. BAM is a block of read-only memory resident in the device.

And much more...

Total topics covered will vary depending on class size, students background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.

Voraussetzungen

Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.

Zielgruppe

The MPC564xA architectural training course is designed for software, hardware, firmware, test engineers, and developers who want to build and test powertrain systems with harsh environment and at the same time not compromise performance.

Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device

FlexyTrain: Unsere Flexibilität – Ihr Plus

Keinen passenden Termin gefunden? Kein Problem: Bei der Planung unserer Kurstermine bieten wir Ihnen ein Höchstmaß an Flexibilität. Im Klartext: Gemeinsam mit Ihnen finden wir einen geeigneten Termin. Sprechen Sie uns an!