MPC5644A (Andorra) Power Architecture

Kursbeschreibung

Course Title: MPC5644A (Andorra) Power Architecture

Target Applications: Industrial and Automotive 1-4 Cylinder gasoline direct injection engines, entry-level diesel engines and entry level transmissions.

Course Description:

A 3-day workshop that covers e200 Power Architecture core, including system exceptions & interrupt handling. It covers the Core memory management unit (MMU) operation and programming. Memory protection, cross-bar switch and all internal/external buses are covered. Also included are details of all on-chip peripherals with emphasis on device timers such as the enhance Time Processor Unit (eTPU), enhanced Modular I/O System (eMIOS).

It includes coverage of the enhanced Queued Analogue-to-Digital Converter (eQADC) operation and programming along with Decimation filters and Reaction Unit operation. It also covers all serial communication interfaces: CAN Bus (FlexCANs), DSPIs, ESCIs (LINFlex) with software examples and optional hands-on labs.

After completing the workshop, the participant will understand the basic concepts of the Power Architecture and all major functional blocks of the MPC5644A device. With hands-on examples and development tools, the participant will be able to program on-chip peripherals and optimize system design.

Participants will be provided: A hard copy of the workshop notes, lab book and textbook. A CDROM of all the lab experiments and demo version of the development tools is also provided.

DETAILED AGENDA:

Day 1

• MPC564xA Overview

• Main Features and Road Map

• MPC5500 and MPC5600 Families Differences

• Power Architecture Core

• Programming Model

• Classic PowerPC Instruction Set Basics

• New Instructions on e200z4

• System exceptions

• Interrupts & Interrupt handling

• Core Timers

• Memory Management Unit (MMU)

• Memory Protection Unit (MPU)

• System Initialization

• Lab examples

Day 2

• System Integration Unit (SIU

• Reset Configuration Half Word (RCHW)

• Reset Resets

• Boot Assist Module (BAM)

• Pad configuration

• Low Power Modes

• Software Initialization Checklist

• Enhanced DMA (eDMA)

• Modular I/O System (eMIOS) with application examples

• Enhanced Timer Processor Unit 2 (eTPU2) with application examples

• Reaction Unit operation and programming

• Lab examples

Day 3

• Queued A/D Converter (eQADC)

• Enhanced Serial Communication

• Interface (eSCI) and LIN Bus

• Deserial Serial Peripheral Interface (DSPI)

• Control Area Net Work (FlexCAN)

• System Memory

• Error Correction Code

• System RAM (SRAM)

• System Flash and Flash protection

• Calibration

• Nexus Summary

Development Tools

• P&E and Codewarrior

Voraussetzungen

Knowledge/experience of some microprocessor/microcontroller is necessary

Zielgruppe

Software and system engineers who need to come up to speed quickly on how to design with this architecture.

Begleitendes Kursmaterial

  • course notes

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