Advanced UVM verification methodology for SoC and FPGA (Deutsch)/(English)

Kursbeschreibung

Advanced UVM verification methodology for SoC and FPGA course covers: The next step of the UVM. The capability to design heterogeneous and complex design platforms and taking ownership for the full flow of the project. Heterogeneous, multicore systems [architectures that combine two or more different types of SoC, FPGA

(MPUs) and microcontrollers (MCUs)] are quickly becoming the defacto architecture in the industry. The quick emergence of these systems can be attributed to a number of factors. reduce the overall size, weight, and power consumption of a system. The practical outcome of this consolidation trend is that modern designs are now being architected to include complex configurations of multiple operating environments onto complex and ever-more powerful processors. The Advanced UVM (Universal Verification Methodology) course lead you throw these new emerging technologies and let you become the project leader from concept design till end of integration.

Day 1:
- Introduction – the next leap
- Layer of abstractions using UVM
- Design Based Model and Model Based Design
- Concept level design
- Multidiscipline systems
- “System of Systems” methodology

Day 2:
- From Single core to multi core design
- Hybrid technologies
- Multi abstraction layers
- Using the „ Best of breed“ approch
- Dealing with System development challenges System Architecture
- Resource share

Day 3:
- System wide communication
- How to debug a system
- How to make changes in system of system environment
- Integration and closure
- Project flow “walkthrough”

Zielgruppe

ASIC/FPGA Verification Eng, which deploy the UVM and SystemVerilog courses.

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