Achieving Timing Closure in Intel FPGAs


This course is taught by Handson Training Oren Hollander in English and it is sponsored by Arrow.

Normal price is 2100€. Arrow is sponsoring 300€ of the seminar fee of each attendee.

This course provides all necessary theoretical and practical know-how to analyze and fix timing failures for variety use cases in Intel FPGAs. In addition, the course goes into great depth and touches upon writing timing constraints for synchronous high speed interfaces such as SDR and DDR. The seminar addresses every aspect of timing failures due to setup and hold negative slack, I/O input/output delays, reset issues, high fanout, global clock networks, over constrained design and timing exceptions. It begins with SDC and timing reports review to highlight which constraints and reports should be written and generated, and when to use each. Then timing closure recommended methodology is discussed with various Quartus Prime tools and advanced settings. Continued by in depth solutions for various timing failures use cases such as too many logic levels, high fanout, confliction SDC assignments, conflicting location assignments, tight timing requirements, clock crossing, and clock skew.

Learn how to write and apply timing constraints for source synchronous interfaces such as SDR and DDR.

The course covers also the Intel FPGAs clocking resources such as GCLK, RCLK, and PCLK, their features and when to use each of them. Timing exceptions are covered in detail (multicycle, false path, clock group).

This 3 day course combines 50% theory with 50% practical work.


1. Understand TimeQuest reports and when to use each

2. Writing correct SDC constraints

3. Efficiently use timing exceptions in SDC

4. Become familiar with the recommended timing closure methodology

5. Analyze and fix various timing problems

6. Use efficiently the chip planner, TimeQuest, RTL and Technology view for

advanced timing analysis

7. Properly constrain and analyze source synchronous interfaces such as


8. Efficiently use the Design Space Explorer tool


Some experience with FPGA design, VHDL


Hardware engineers who develop FPGAs and would like to enhance their skills

Begleitendes Kursmaterial

  • course notes


  • 19.03.2018 - 21.03.2018 : 1800 €

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