ARM / i.MX 51 (Deutsch)/(English)

Kursbeschreibung

The i.MX51 is a 4-day class lecture covering the main features of the i.MX51 architecture, operation and programming.

This course covers the ARM Cortex A8™ platform including programming model exceptions and interrupt handling, interrupt controller, instruction set, Application Processor level 1 and level 2 caches, cross-bar switch, Memory Management Unit (MMU), application processor I/O peripherals, Smart Direct Memory, Access Control, Multi-master Multi-Memory Interfaces (M4IF), Graphics and Image Processing unit (IPU) and system wide integration.

Target Applications: Wireless device running computationally intensive multimedia applications such as portable media players and portable navigation devices. Target devices also include feature rich smart phones, digital video recorders, digital cameras, mobile gaming consoles, mobile multimedia players and many other mobile wireless applications.

Themenschwerpunkte

  • System Overview
    • Platform Overview
    • ARM Cortex ™ Platform overview
  • System-wide Connectivity
  • ARM Cortex A8 CoreARM Cortex A8 Core
    • Instruction Pipe
    • Branch Prediction
    • Programming Model
    • Register Banking
    • Stacking
    • ARM® -Thumb Engines and Switching
    • ARM Instruction Set Overview
  • Thumb Programming Model and Instruction Set
  • NEON Overview
    • Programming Model
    • Instruction Set
  • System Caches
    • Level 1 Instruction and Data Caches
    • Concept
    • Organization
    • Cache Operation and programming
  • Level 2 Cache Organization and Operation
  • Memory Management Unit (MMU)
    • Concept
    • MMU Architecture
    • Address Translation
    • Protection
    • Table-walk
    • System Operation and Programming
  • Application Processor Peripherals
    • External Interrupts
    • KeyPad Port
    • Real-time Clock
    • Pulse Width Modulator (PWM)
    • General Purpose Timer (GPT)
    • Enhanced Periodic Interrupt Timer
    • Watchdog Timer
  • I/O Muxing
    • GPI/O
    • Pin Assignments and Configuration
  • Audio Muxing
  • Sony Phillips Digital Interface (SPDIF)
  • Smart Direct Memory Access Controller (SDMA)
    • Overview
    • Concept
    • Shared Resources
    • Programming Model
    • I/O Requests
    • Operation
    • Programming
  • System Clock Generation
    • Clocks and Reset Sources
    • System Clock Distribution
    • PLL Programming and Operation
  • Low Power Modes
  • External Interfaces
    • M4IF – Multi-master Multi-Memory Interface
    • Wireless Interface (WIEM)
    • NAND Flash Controller
    • DDR
    • Advance Technology Attachment (ATA)
  • System Boot
    • Internal RAM and Boot ROM
    • Graphics Memory
    • Red Boot
  • IC Identification Module (IIM)
  • Video and Graphics
    • IPU Overview and Basic Operation
    • Video Capturing
    • Preprocessing
    • Resizing
    • De-blocking and De-ringing
    • Color Space Conversion
    • Inversion and Rotation
  • Graphic Processing Unit
    • MIPI HSC
  • More i.MX51 Peripherals
    • SIM
    • USB and PHY Interface
    • MIPI SLIMBUS
  • Shared Peripherals
    • CSPI and eCSPI
    • UARTs
    • SSI
    • IIC
    • HS IIC
    • FIR
    • O-WIRE
  • Power Management IC and Connectivity
  • Demo using PDK Evaluation Board
  • Summary

Voraussetzungen

Due to the high degree of functionality and integration of this device, the student is encouraged to gain some familiarity beforehand by reviewing current Freescale documentation for this product. Introductory level web-based training materials are available at www.freescale.com/training. Search on i.MX51 for a list of available overview materials.

Zielgruppe

Application Software and system engineers who need to come up to speed quickly on how to design with this architecture.

Begleitendes Kursmaterial

  • course notes

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