VP Workshop

Kursbeschreibung

Authors or Presenters:

Eyck Jentzsch, MINRES Technologies GmbH

Virtual Prototype/Platform – what it is and what it is good for

Todays electronics devices are dominated by system on chips (SoCs) where software is more and more dominant in terms of amount and effort to create and validated it. To allow for short product cycles virtual prototypes and platforms are developed to start SW development even before silicon is available. But the availability of VPs and its components allows changing the development approach in other areas as well.

The work shop aims to spotlight on virtual prototype/platform (VP) implementation and use cases not only in the semiconductor vendor domain rather also at its customers.

The first part focuses on the clarification of the term VP as well as the building blocks and tools used and needed to implement them. The second part will outline the various use cases of a VP at semiconductor vendor and customer premises. Various groups can be identified like IP authors, platform authors/IP integrators, and platform users/SoC integrators/system integrators, which use VPs (amongst others) for architectural exploration, performance analysis and validation, functional verification and early software (esp. firmware) development. But also the use of VPs to change the system software development approach of system integrators and users of the SoC will be highlighted (prime example here is the Android emulator). The last part is going to outline the advantages of using a VP in the various aforementioned use cases over other approaches like FPGA prototyping, emulation or HIL. It will also point out the limitations of VPs as well how various approaches augment each other.

The presentations and discussions will be accompanied with demonstrations to highlight key features where applicable.

What is a VP (20 min)

3. virtual prototype vs. virtual platform

• virtual prototype – is in development and does not have final shape. Quick change and comprehensive analysis means, used for optimal SoC design wrt. power/area/speed

• virtual platform – represents a SoC in its final shape, aims at accuracy, speed, and completeness, used for (e)SW development

4. building blocks of a VP

• standards (? Rocco)

o C++/SystemC

o IP-XACT, RDL, SysML

o SystemVerilog

• modeling techniques (? Eyck)

o behavioral/untimed

o functional/loosly timed

o cycle-accurate/approximately timed

o register-transfer-level

• IPs (? Rocco)

o whole eco-system of producer & consumer

o quite often consumer is also producer

o e.g. ARM, Synopsys, Cadence, Netspeed Systems

• tools (? Eyck)

o SNPS processor designer, Virtualizer

o Cadence System Studio

o Mentor Vista

o Matlab/Simulink

o VLAB Works

o Xilinx Vivado

o ARM Carbon Model Studio, SoC Designer Plus,

Uses of VP (40min)

• semiconductor vendor uses (? Rocco/Eyck)

o architectural exploration

o performance analysis & validation

o functional verification

o high level synthesis (?)

o early SW (driver, HAL & OS) development

• customer uses (? Eyck)

o early SW (driver, HAL, OS, application) development

o debug & analysis tool for regular SW development

o TDD & CI infrastructure element

Advantages and Limitations (20min)

• easy reconfiguration

• Scalability

• Observability [with TLM recording]

• Fault injection & simulation

• Simulation speed

• Accuracy

Q&A (10min)

Voraussetzungen

Basic knowledge of programming Languages

Zielgruppe

Engineers who are new to or interested in learning about VP

Begleitendes Kursmaterial

  • course notes

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