MPC5643L (Leopard) Power Architecture

Kursbeschreibung

Course Title: MPC5643L (Leopard) Power Architecture

Target Applications: Industrial and Automotive 1-4 Cylinder gasoline direct injection engines, entry-level diesel engines and entry level transmissions.

Course Description:

This 3 day course offers coverage of e200z4 Dual-Core Power Architecture, Memory Management Unit, Memory Protection Unit (MPU), Instruction Cache, Crossbar switch and all Internal Buses, Redundancy Checker (CR), Fault Collection & Control Unit (FCCU), Clock Generation, Power Modes and Power Management Unit.

The course provides lengthy discussion and coverage of the motor control peripheral set with emphasis on the FlexPWM, Cross Trigger Unit (CTU) and the Analogue-to-Digital Converter (ADC) and how they interact with each other. It includes coverage of the Serial I/O Modules such as LINFlex, FlexCAN and DSP interfaces, Enhanced Direct Memory Controller (eDMA)). It also covers two cores running in a clock-accurate lock-step mode with emphasis on safety-critical features.

Safety Integrity Level to meet ASIL26262 standards is also covered.

The course will have hands-on lab examples using the MPC5643L Evaluation Boards (EVBs).

Upon customer request we will provide a complete lecture and demo on the Freescale’s Motor Control Development Toolbox, based on MATLAB, Simulink and Embedded Coder, to generate C-code from simulation models.

The toolbox contains peripheral and optimized math/motor control blocks, and enables software/processor-in-the-loop verification support and utilities for MCU programming. It also enables real-time monitoring and parameter tuning using FreeMASTER software.

Participants will be provided: A hard copy of the workshop notes, lab book and textbook. A CDROM of all the lab experiments and demo version of the development tools is also provided.

After completing the workshop, the participant will understand the basic concepts of the Dual Core Power Architecture and all major functional blocks of the Leopard (MPC5643L) device.

DETAILED AGENDA:

Day 1

MPC5643L Dual Core

• Main Features & Dual Core Basics

• Power Architecture Core

• Programming Model (Z4 Core)

• Classic PowerPC Instruction Set

• Signal Processing Engine

• Variable-Length Encoding (VLE)

• Core Exceptions and Handling

• Interrupt Controller

• Programmer’s Model

• Context Switching (New Instructions)

• Interrupts Handling

• Memory Management Unit (MMU)

• System Cache (Instruction Cache)

• Memory Protection Unit (MPU)

• Enhanced DMA (eDMA2)

System Memory

• SRAM

• LC Flash Organization and operation

• Erase and Program Sequence

• Error Correction, Detection & Error Reporting

Day 2

• System Clock Generation and Initialization

• Internal Oscillator,

• Phase Locked Loops (PLLs)

• System Clock Generation

• Clock Monitor Unit (CMU)

• Pad (Pin) Assignment and Configuration

• Boot-assist Module (Boot Sequence)

• External Bus Interface (EBI)

• System Reset Sources

• Device Configuration

• Reset Handling

• Software Initialization Checklist after Power and system Resets

• Two cores running in a clock-accurate lock-step mode (DPM)

• Concept

• Description

• Detection and Correction

• System Timers

• Periodic Interrupt Timers (PIT)

• STM

• SWT

• Serial I/O

• UART and LINFlex Bus

• DSPI

• FlexCAN2

• Flexray Overview

Day 3

Motor Control Peripheral Set

• eTimer

• FlexPWM Timer

• A/D Converter (ADC)

• Cross Trigger Unit (CTU)

Functional Safety

Tools

• Nexus Summary

Voraussetzungen

Knowledge/experience of some microprocessor/microcontroller is necessary

Zielgruppe

Software and system engineers who need to come up to speed quickly on how to program and design with the MPC5643L Devices.

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